1. Field of the Invention
The present invention relates to a package, for semiconductor devices, for mounting semiconductor elements. More specifically, the invention relates to a package for semiconductor devices formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface thereof, a portion for mounting a semiconductor element, or, further, having one or a plurality of insulating resin layers on the upper surface of the laminate of many layers and having, on the upper surface of the uppermost insulating resin layer thereof, a portion for mounting a semiconductor element, featuring improved junction strength in the junction portion between the semiconductor element and the semiconductor package. The present invention further relates to an interposer disposed between the semiconductor element and the semiconductor package.
2. Description of the Related Art
In many cases, in the conventional art, an insulating resin has been used alone as a material of insulating resin layers for a multi-layer package for semiconductor devices, comprising a laminate of many layers obtained by alternately laminating a plurality of conducting layers and insulating resin layers and, particularly, as a material of insulating resin layers for a multi-layer semiconductor substrate or a semiconductor package of which all the layers are formed by a build-up process. Therefore, the package for mounting the semiconductor element by itself has a small strength but a large coefficient of linear thermal expansion. In particular, if the coefficient of linear thermal expansion of the insulating resin layer is greatly different from the coefficient of linear thermal expansion of the semiconductor element that is mounted, thermal stress occurs between the semiconductor element and the package at the time of mounting the semiconductor element on the package in the step of reflowing the solder, causing a problem in that the package or the semiconductor element is damaged.
In order to enhance the strength of the semiconductor package, further, a multi-layer substrate is often produced by using an insulating resin layer by incorporating a glass cloth therein. When the multi-layer resin substrate incorporating the glass cloth is used, however, the via-holes or through holes tend to be deformed at the time of being perforated in the package by the irradiation with a laser beam. When the through holes are to be plated, further, the plating is not favorably accomplished. In such a case, too, the coefficient of linear thermal expansion of the insulating resin layer is about 15 ppm at the smallest which, however, cannot be brought close to the coefficient of linear thermal expansion of the semiconductor element itself any more.
In order to reinforce the semiconductor package, further, the package may be surrounded by a reinforcing material (stiffener). In general, however, the package has a coefficient of linear thermal expansion which is greater than that of the conventional reinforcing member. Therefore, when the semiconductor element is to be mounted on the package by reflowing the solder, the central portion of the package expands more than the outer peripheries making it difficult to accomplish a favorable electric connection to the semiconductor element.
If viewed from the side of the semiconductor element, further, the material used as the semiconductor element, usually, has a low dielectric constant and is very brittle and tends to be easily broken. Therefore, the stress must be decreased as much as possible in the junction portion between the semiconductor element and the package.
Related arts have been disclosed in the following documents. For example, Japanese Unexamined Patent Publication (Kokai) No. 11-163208 discloses the use of a prepreg obtained by using a nonwoven fabric of a liquid crystal polyester as a base material of multi-layer printed board, and impregnating it with a thermosetting resin component. Japanese Unexamined Patent Publication (Kokai) No. 2000-31642 discloses the use of a liquid crystal polyester or a polyarylate as a resin for forming an insulating layer on the built-up multi-layer circuit board, and roughening of the surface of the insulating resin sheet by sand-blasting. Further, Japanese Unexamined Patent Publication (Kokai) No. 2002-16173 discloses the insulating layer of the semiconductor device that is constituted by using a resin and a glass cloth, a nonwoven fabric of a glass, a polyamide-type nonwoven fabric or a liquid crystal polymer-type nonwoven fabric.
Japanese Unexamined Patent Publication (Kokai) No. 2000-323613 discloses a multi-layer substrate for semiconductor devices contriving the shape of the via-holes for interlayer connection in order to flatten the surface for mounting the semiconductor element as much as possible and to decrease the thickness as much as possible. Japanese Unexamined Patent Publication (Kokai) No. 2001-36253 discloses an insulating resin layer that is partly constituted by using a resin layer of a low elasticity to absorb stress generated due to a difference in the coefficient of thermal expansion from an electronic part such as a semiconductor element that is mounted. Further, Japanese Unexamined Patent Publication (Kokai) No. 2001-274556 discloses laminating a thermally expanding buffer sheet having a coefficient of thermal expansion of 6 to 12 ppm integrally on a printed wiring board on which a surface-mounting part is to be mounted to obtain a printed wiring board for surface mounting maintaining excellent reliability in the connection to the surface-mounted part. Japanese Unexamined Patent Publication (Kokai) No. 2002-83893 discloses a multi-layer wiring structure film having improved flatness using a metal base as a reinforcing material, laminating a multi-layer wiring structure film on a metal base made of a metal plate and having an opening for inserting a semiconductor element, inserting the semiconductor element in the opening of the metal base, and connecting a flip chip.
According to the prior art, as described above, problems have not been solved to a sufficient degree in regard to forming via-holes and through holes by using a laser beam, adhesion of plating in the through holes and strength of the semiconductor package itself. In the step of producing a semiconductor device, further, when the semiconductor element is to be mounted on the package by reflowing the solder, the central portion of the package expands more than the outer peripheries thereof due to a difference in the coefficient of linear thermal expansion between the central portion of the package on where the semiconductor element is mounted and the outer peripheries thereof due to the temperature, and stress occurs between the semiconductor element and the package, thus leaving problems. The problem has not been fully solved, either, concerning the stress between the semiconductor element and the package as a result of thermal expansion when the semiconductor element is in operation.